Icarus Verilog
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module

binary_encoder_8to3 (

input [2:0] A,

output reg [2:0] Y

);

always @(*)

begin

case(A)

3'b000: Y = 3'b000;

3'b001: Y = 3'b001;

3'b010: Y = 3'b010;

3'b011: Y = 3'b011;

3'b100: Y = 3'b100;

3'b101: Y = 3'b101;

3'b110: Y = 3'b110;

3'b111: Y = 3'b111;

default: Y = 3'b000; // Default case

endcase

end

endmodule

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