This is an update to the Icarus Verilog 0.9 release series. If you are new to v0.9 in general, then you may want to refer back to these older release notes since this page only covers the differences between v0.9.4 and v0.9.5.
Major New Features Edit
Within the v0.9 series we try to keep the major changes to a minimum, but some new features are allowed in if we feel that they do not risk the stability of the branch or of Verilog programs that use this compiler.
Language Coverage Edit
- Added the stochastic analysis system tasks (queue).
Language Extensions Edit
- Add support to the FST dumper to save a modules definition name.
- A single % at the end of a format is interpreted as %%.
General Bug Fixes Edit
- Fix some issues with the power operator.
- Reworked $sscanf() and $fscanf() to fix bugs and to support everything in the standard except for the %u, %v and %z format codes. These will be added at a later date.
- Fixed a DLL search patch issue on windows.
- Report an error on windows if the executable path is malformed.
- A single primitive gate input can be passed a vector (only the LSB is used).
- Some specparam improvements (full 2001/2005 support is still missing).
- Fix elaboration of multiple output primitives (tran, pull, buf and not).
- Fix the compiler comparison of some negative values.
- Fix problems in vvp when procedurally dividing certain large values.
- Avoid a minor buffer overflow in the $display code.
- Update the dumpers to the latest from GTkWave.
- Add a correct tf_getlongsimtime() routine.
- Add the ability to iterate over the path terms of a mod path.
- Numerous other bug fixes (the complete details can be found in the commit logs for the v0_9-branch of iverilog on github).
Things That Still Don't Work Edit
This isn't necessarily a complete list of missing features, but this should at least list the missing features that you are likely to encounter.
Missing Language Features Edit
- PLA modeling system tasks.
- Multi-dimensional arrays.
- Timing checks (they are currently ignored).
- The various pulse limits/controls.
- specparam with a range, outside a specify block, back-annotation, or referencing another specparam.
- Constant user functions.
- Net delays.
- trireg nets (capacitive networks).
- Inertial delays from the PLI
Bugs fixed/enhancements in development that will not be added to V0.9 Edit
This list has become too large to publish. Please see the git commit logs for the details.
Bugs Still Pending Edit
There are known bugs that are still pending. Some may be fixed in later releases of 0.9, but most will have to wait for the next major release. See the bug tracker for the complete list.
Where to Get Icarus Verilog 0.9.5 Edit
The source tar file and precompiled packages for select systems are available from the main ftp site: <ftp://ftp.icarus.com/pub/eda/verilog/v0.9/>. If you don't find what you are looking for there please look on the standard software distribution site(s) for your operating system if such a thing exists. A package for Microsoft Windows can be found here: <http://bleyer.org/icarus>.