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Release Notes Icarus Verilog 0 9 3

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This is an update to the Icarus Verilog 0.9 release series. If you are new to v0.9 in general, then you may want to refer back to these older release notes since this page only covers the differences between v0.9.2 and v0.9.3.

Major New Features Edit

Within the v0.9 series we try to keep the major changes to a minimum, but some new features are allowed in if we feel that they do not risk the stability of the branch or of Verilog programs that use this compiler.

Language Coverage Edit

  • Remove obsolete VAMS $log function.
  • Add a warning that synthesis is not currently being maintained when -S is used.
  • Fix $dist_erlang to use the correct function.
  • Named blocks now keep their scope information.
  • It is now an error to try to take the edge of a named event.
  • Add the correct version information to the data structure returned by the PLI vpi_get_vlog_info() call.

Language Extensions Edit

  • Add FST dumper.
  • Add +timescale to the command file.
  • Add ability to automatically perform bit <-> real conversion for module inputs/outputs where this makes sense.
  • Add optional warnings for out of range bit/part selects.
  • Add $info(), $warning() and $error() as aliases for $display.

General Bug Fixes Edit

  • Fix problems in the variable index handling for bit, indexed part and array word selects.
  • Fix some problems in constant bit/part selects.
  • Fix non-blocking real to vector conversions.
  • Fix the ternary operator with real arguments to support an infinite amount of tail recursion.
  • Fix $() substitution in a command file.
  • Add support for compiling using gcc-4.5.
  • Add support for compiling using SUNPro compiler (OpenSolaris).
  • Update and fix some LXT/LXT2 dumper issues.
  • Switch to C99/C++ header files.
  • Fix a number of compiler warnings for various systems/compiler versions.
  • Fix some memory leaks.
  • Make the code -Wshadow clean and add -Wshadow to the normal compilation flags.
  • Add some minor SDF enhancements (development has even more fixes).
  • Fix a line number issue with // style comments.
  • Do not remove unused module ports.
  • Fail gracefully for recursive or invalid parameter definitions.
  • Fix the behavior of a release when a variable/net is not currently forced.
  • Numerous other bug fixes (the complete details can be found in the commit logs for the v0_9-branch of iverilog on github).

Things That Still Don't Work Edit

This isn't necessarily a complete list of missing features, but this should at least list the missing features that you are likely to encounter.

Missing Language Features Edit

  • PLA modeling system tasks.
  • Stochastic analysis system tasks.
  • Multi-dimensional arrays.
  • Timing checks (they are currently ignored).
  • The various pulse limits/controls.
  • specparam with a range, outside a specify block, back-annotation, or referencing another specparam.
  • Constant user functions.
  • Net delays.
  • trireg nets (capacitive networks).
  • Inertial delays from the PLI

Bugs fixed/enhancements in development that will not be added to V0.9 Edit

  • The way VVP handles nets has been reworked. This allows force, etc. to work correctly.
  • Reworked the initial value propagation and make the value more standard.
  • A uwire with multiple drivers will now be reported as an error during code generation.
  • Added better support for SDF back annotation and delay selection.
  • Added delay support to tranif gates and other improvements.
  • Added support for two variable delays where appropriate.
  • Added support for a UDP with a variable delay.
  • Added support for overriding a parameter from the command line/command file.
  • Better/more efficient support of signed or undefined variable selects.
  • Added non-blocking assignment to a real array.
  • Add full support for SystemVerilog $fatal, $error, $warning and $info.
  • Added SystemVerilog timeunit and timeprecision.
  • Added all the Verilog-AMS and SystemVerilog keywords when appropriate.
  • A number of VHDL generator fixes.
  • Added support for `celldefine and vpiCellInstance.
  • Added support for vpiUserSystf iteration, vpi_get_systf_info(), etc.
  • Some general speedup improvements.
  • A number of other bug fixes.

Bugs Still Pending Edit

There are known bugs that are still pending. Some may be fixed in later releases of 0.9, but most will have to wait for the next major release. See the bug tracker for the complete list.

Where to Get Icarus Verilog 0.9.3 Edit

The source tar file and precompiled packages for select systems are available from the main ftp site: <ftp://ftp.icarus.com/pub/eda/verilog/v0.9/>. If you don't find what you are looking for there please look on the standard software distribution site(s) for your operating system if such a thing exists. A package for Microsoft Windows can be found here: <http://bleyer.org/icarus>.

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