This is an update to the Icarus Verilog 0.9 release series. If you are new to v0.9 in general, then you should refer back to those release notes as well, as these notes are for the differences between v0.9.1 and v0.9.2.
Major New Features Edit
Within the v0.9 series we try to keep the major changes to a minimum, but some new features are allowed in if we feel that they do not risk the stability of the branch or of Verilog programs that use this compiler.
Language Coverage Edit
We have added to v0.9.2 some IEEE1364-2005 features that v0.9.1 lacked. So language coverage is better with this release. Notable improvements include:
- Implement $fread and $ferror,
- Replace the nonstandard $log function with $log10,
- Add support for 2/3 constant delays to continuous assignments,
- Implement the VPI cbAtStartOfSimTime callback,
- Implement `resetall,
- Add support for `unconnected_drive,
- Add 2001-noconfig language support,
- Ignore more timing check syntax in specify blocks,
- Support dump of named events.
Language Extensions Edit
There are also some new language extensions that v0.9.2 adds:
- Implement the $readmempath() system task to set the search path for $readmemX tasks,
- Allow $dumpvars to accept array members for dumping,
- Relax limits on the number of open files,
- Enhance support for arrays of real variables and nets.
General Bug Fixes Edit
There are also many bug fixes. Some prominent examples are:
- Fix recursive instantiation of modules within generate schemes,
- Better checks for name space collisions,
- Flush I/O streams when entering interactive mode,
- Fix a variety of select/mixed-endian bugs,
- Fix handling of spaces in file names,
- Fix handling of installation suffixes on Windows.
Things That Still Don't Work Edit
This isn't necessarily a complete list of missing features, but this should at least list the missing features that you are likely to encounter.
Missing Language Features Edit
- Constant user functions
- Net delays
- trireg nets (capacitive networks)
- Multi-dimensional arrays
- Timing checks (they are silently ignored)
- The various pulse limits (they are silently ignored)
- The $fmonitor() family of system task
- design configuration
- The `pragma compiler directive
- `celldefine information is not passed to the run time. It works as expected in the development version.
- PLA modeling system tasks
- Stochastic analysis system tasks
- Various VPI limitations
iverilog or vvp will issue an error message and quit for most of these.
Bugs Still Pending Edit
There are known bugs that are still pending. Some will be fixed in later releases of 0.9, and some will have to wait for the next major release. See the bug tracker for the current list.
Where to Get Icarus Verilog 0.9.2 Edit
The source tarball is available from the main ftp site: <ftp://ftp.icarus.com/pub/eda/verilog/v0.9/>. There are also precompiled packages for select systems. Or look to the standard software distribution sites for your operating system if such things exist for your distribution.