Iverilog Flags
From Icarus Verilog
The iverilog command is the compiler/driver that takes the Verilog input and generates the output format, whether the simulation file or synthesis results. This information is at least summarized in the iverilog man page distributed in typical installations, but here we try to include more detail.
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[edit] General
These flags affect the general behavior of the compiler.
[edit] -c<cmdfile>
This flag selects the command file to use. The command file is an alternative to writing a long command line with a lot of file names and compiler flags.
[edit] -d<flag>
Enable compiler debug output. The flag is one of these debug classes:
- scope
- eval_tree
- elaborate
- synth2
Any flag value other then the above will be ignored. The '-d' flag can be repeated on the command line as needed to enable the desired flags.
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The '-d' flag is new in 0.9 snapshots as of 2008. This flag is rarely used in normal operation, it is only useful for debugging problems with the compiler itself. |
[edit] -g<generation flag>
The generation is the compiler language, and specifies the language level and extensions to use during the compile. The language level can be selected by a major level selector, and by controlling various features. Various "-g" flags can be combined. For example, to get Verilog 2001 without specify support, use "-g2 -gno-specify". The default is generally to include the most.
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This describes the -g flag as implemented starting in recent snapshots leading to the 0.9 release. The 0.8 stable release supports this flag, but only the "1", "2" and "2x" flags. |
- 1
Level-1 verilog, based on the IEEE1364-1995 standard.
- 2
Level-2 verilog, based on the IEEE1364-2001 standard.
- 2x
Level-2 verilog plus Icarus Verilog extensions.
- verilog-ams
This flag enables Verilog-AMS features that are supported by Icarus Verilog. (This is new as of 5 May 2008.)
- specify/no-specify
Turn on or off support for specify block timing controls. When off, specify blocks are parsed but ignored. When on, specify blocks cause timing path and timing checks to be active.
- xtypes/no-xtypes
Enable or disable support for extended types. Enabling types allows for new types and type syntax that are Icarus Verilog extensions.
- io-range-error/no-io-range-error
When enabled the range for a port and any associated net declaration must match exactly. When disabled a scalar port is allowed to have a net declaration with a range (obsolete usage). A warning message will be printed for this combination. All other permutations are still considered an error.
[edit] -o<path>
Specify the output file. The <path> is the name of the file to hold the output. The default is "a.out".
[edit] -s topmodule
Specify the top level module to elaborate. Icarus Verilog will by default choose modules that are not instantiated in any other modules, but sometimes that is not sufficient, or instantiates too many modules. If the user specifies one or more root modules with "-s" flags, then they will be used as root modules instead.
[edit] -Tmin|typ|max
Select the timings to use. The Verilog language allows many timings to be specified as three numbers, min:typical:max, but for simulation you need to choose which set to use. The "-Tmin" flag tells the compiler to at elaboration time choose "min" times. The default is "-Ttyp".
[edit] -y<libdir>
Append the directory to the library module search path. When the compiler finds an undefined module, it looks in these directories for files with the right name.
[edit] Preprocessor Flags
These flags control the behavior of the preprocessor. They are similar to flags for the typical "C" compiler, so C programmers will find them familiar.
[edit] -E
This flag is special in that it tells the compiler to only run the preprocessor. This is useful for example as a way to resolve preprocessing for other tools. For example, this command:
% iverilog -E -ofoo.v -DKEY=10 src1.v src2.v
runs the preprocessor on the source files src1.v and src2.v and produces the single output file foo.v that has all the preprocessing (including header includes and ifdefs) processed.
[edit] -D<macro>
Assign a value to the macro name. The format of this flag is one of:
-Dkey=value -Dkey
The key is defined to have the given value. If no value is given, then it is assumed to be "1". The above examples are the same as these defines in Verilog source:
`define key value `define key
[edit] -I<path>
Append directory <path> to list of directories searched for Verilog include files. The -I switch may be used many times to specify several directories to search, the directories are searched in the order they appear on the command line.
[edit] Target Flags
These flags control the selection and behavior or target code generators.
[edit] -t<target>
Select the target code generator. The default is "-tvvp" to select the vvp simulation format. The following targets exists:
- null
The null target causes no code to be generated. It is useful for checking the syntax of the Verilog source.
- vvp
This is the default. The vvp target generates code for the vvp runtime. The output is a complete program that simulates the design but must be run by the vvp command
- xnf
This is the Xilinx Netlist Format used by many tools for placing devices in FPGAs or other programmable devices. This target is obsolete, use the fpga target instead.
- fpga
This is a synthesis target that supports a variety of fpga devices, mostly by EDIF format output. The Icarus Verilog fpga code generator can generate complete designs or EDIF macros that can in turn be imported into larger designs by other tools. The fpga target implies the synthesis -S flag.
[edit] Compiler Debug Flags
There are a few flags that are only of use for debugging the compiler. They are not generally useful.
