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The iverilog command is the compiler/driver that takes the Verilog input and generates the output format, whether the simulation file or synthesis results. This information is at least summarized in the iverilog man page distributed in typical installations, but here we try to include more detail.


General Edit

These flags affect the general behavior of the compiler.

-c<cmdfile> Edit

This flag selects the command file to use. The command file is an alternative to writing a long command line with a lot of file names and compiler flags. See the Command File Format page for more information.

-d<flag> Edit

Enable compiler debug output. The flag is one of these debug classes:

  • scope
  • eval_tree
  • elaborate
  • synth2

Any flag value other then the above will be ignored. The '-d' flag can be repeated on the command line as needed to enable the desired flags.

The '-d' flag is new in 0.9 snapshots as of 2008. This flag is rarely used in normal operation, it is only useful for debugging problems with the compiler itself.


-g<generation flag> Edit

The generation is the compiler language, and specifies the language level and extensions to use during the compile. The language level can be selected by a major level selector, and by controlling various features. Various "-g" flags can be combined. For example, to get Verilog 2001 without specify support, use "-g2 -gno-specify". The default is generally to include the most.

This describes the -g flag as implemented starting in recent snapshots leading to the 0.9 release. The 0.8 stable release supports this flag, but only the "1", "2" and "2x" flags.


  • 1

Level-1 verilog, based on the IEEE1364-1995 standard. (Suggest using -g1995 instead.)

  • 2

Level-2 verilog, based on the IEEE1364-2001 standard. (Suggest using -g2001 instead.)

  • 2x

Level-2 verilog plus Icarus Verilog extensions.

  • 1995

This flag enables the IEEE1364-1995 standard.

  • 2001

This flag enables the IEEE1364-2001 standard.

  • 2001-noconfig

This flag enables the IEEE1364-2001 standard with config file support disabled. This eliminates the config file keywords from the language and so helps some programs written to older 2001 support compile.

  • 2005

This flag enables the IEEE1364-2005 standard. This is default enabled after v0.9.

  • 2009

This flag enables the IEEE1800-2009 standard, which includes SystemVerilog. The SystemVerilog support is not present in v0.9 and earlier. It is new to git master as of November 2009. Actual SystemVerilog support is ongoing.

  • 2012

This flag enables the IEEE1800-2012 standard, which includes SystemVerilog. Actual SystemVerilog support is ongoing.

  • verilog-ams

This flag enables Verilog-AMS features that are supported by Icarus Verilog. (This is new as of 5 May 2008.)

  • assertions/no-assertions

Enable/Disable SystemVerilog assertion syntax. The -gno-assertions flag may be useful for compiling Verilog code written before SystemVerilog that has some assertion keywords.

  • relative-include/no-relative-include

[?]

  • specify/no-specify

Turn on or off support for specify block timing controls. When off, specify blocks are parsed but ignored. When on, specify blocks cause timing path and timing checks to be active.

  • strict-ca-eval/no-strict-ca-eval

[?]

  • strict-expr-width/no-scrict-expr-width

[?]

  • xtypes/no-xtypes

Enable or disable support for extended types. Enabling types allows for new types and type syntax that are Icarus Verilog extensions.

  • io-range-error/no-io-range-error

When enabled the range for a port and any associated net declaration must match exactly. When disabled a scalar port is allowed to have a net declaration with a range (obsolete usage). A warning message will be printed for this combination. All other permutations are still considered an error.

-l <path> Edit

Add the specified file to the list of source files to be compiled, but mark it as a library file. All modules contained within that file will be treated as library modules, and only elaborated if they are instantiated by  other modules in the design.

NOTE: The "-l" option is new as of 2 October 2016. It will become available in releases and snapshots made after that date.

-o<path>Edit

Specify the output file. The <path> is the name of the file to hold the output. The default is "a.out".

-S (v0.8 only) Edit

Activate synthesis. This flag tells the compiler to do what synthesis it can do before calling the code generator. This flag is rarely used explicitly, and certain code generators will implicitly enable this flag.

NOTE: Icarus Verilog release 0.9 and later do not support synthesis, even though this flag is still present. Please do not expect this flag to do anything useful for you in 0.9 or later releases.

-v Edit

Be verbose. Print copyright information, progress messages, and some timing information about various compilation phases.

(New in snapshots after 2014-12-16) If the selected target is vvp, the -v switch is appended to the shebang line in the compiler output file, so directly executing the compiler output file will turn on verbose messages in vvp. This extra verbosity can be avoided by using the vvp command to indirectly execute the compiler output file.

-V Edit

Print the version information. This skips all compilation. Just print the version information, including version details for the various components of the compiler.

-W<warning class> Edit

Enable/disable warnings. All the warning types (other then all) can be prefixed with no- to disable that warning.

  • all

This enables almost all of the available warnings.

  • implicit

This enables warnings for creation of implicit declarations. For example, if a scalar wire X is used but not declared in the Verilog source, this will print a warning at its first use.

  • implicit-dimensions

This enables warnings for the case where a port declaration or a var/net declaration for the same name is missing dimensions. Normally, Verilog allows you to do this (the undecorated declaration gets its dimensions form the decorated declaration) but this is no longer common, and some other tools (notable Xilix synthesizers) do not handle this correctly.

This flag is supported in release 10.1 or master branch snapshots after 2016-02-06.

  • portbind

This enables warnings for ports of module instantiations that are not connected properly, but probably should be. Dangling input ports, for example, will generate a warning.

  • select-range

This enables warnings for constant out-of-bound selects. This includes partial or fully out-of-bound select as well as a select containing a 'bx or 'bz in the index.

  • timescale

This enables warnings for inconsistent use of the timescale directive. It detects if some modules have no timescale, or if modules inherit timescale from another file. Both probably mean that timescales are inconsistent, and simulation timing can be confusing and dependent on compilation order.

  • infloop

This enables warnings for always statements that may have runtime infinite loops (i.e. has paths with zero or no delay). This class of warnings is not included in -Wall and hence does not have a no- variant. A fatal error message will always be printed when the compiler can determine that there will definitely be an infinite loop (all paths have no or zero delay).

When you suspect an always statement is producing a runtine infinite loop, use this flag to find the always statements that need to have their logic verified. it is expected that many of the warnings will be false positives, since the code treats the value of all variables and signals as indeterninite.

  • sensitivity-entire-vector

This enables warnings for when a part select with an "always @*" statement results in the entire vector being added to the implicit sensitivity list. Although this behavior is prescribed by the IEEE standard, it is not what might be expected and can have performance implications if the vector is large.

  • sensitive-entire-array

This enables warnings for when a word select with an "always @*" statement results in the entire array being added to the implicit sensitivity list. Although this behavior is prescribed by the IEEE standard, it is not what might be expected and can have performance implications if the array is large.

  • floating-nets

This enables warnings for nets that are present but have no drivers. This flag is supported in version 11 or later as of 2015-10-01.

-y<libdir> Edit

Append the directory to the library module search path. When the compiler finds an undefined module, it looks in these directories for files with the right name.

-Y<libdir> Edit

[?]

Preprocessor Flags Edit

These flags control the behavior of the preprocessor. They are similar to flags for the typical "C" compiler, so C programmers will find them familiar.

-E Edit

This flag is special in that it tells the compiler to only run the preprocessor. This is useful for example as a way to resolve preprocessing for other tools. For example, this command:

% iverilog -E -ofoo.v -DKEY=10 src1.v src2.v

runs the preprocessor on the source files src1.v and src2.v and produces the single output file foo.v that has all the preprocessing (including header includes and ifdefs) processed.

-D<macro> Edit

Assign a value to the macro name. The format of this flag is one of:

-Dkey=value
-Dkey

The key is defined to have the given value. If no value is given, then it is assumed to be "1". The above examples are the same as these defines in Verilog source:

`define key value
`define key

-I<path> Edit

Append directory <path> to list of directories searched for Verilog include files. The -I switch may be used many times to specify several directories to search, the directories are searched in the order they appear on the command line.

Elaboration Flags Edit

These are flags that pass information to the elaboration steps.

=== -P<symbol>=<value>

Define a parameter using the defparam behavior to override a parameter values. This can only be used for parameters of root module instances.

-s topmodule Edit

Specify the top level module to elaborate. Icarus Verilog will by default choose modules that are not instantiated in any other modules, but sometimes that is not sufficient, or instantiates too many modules. If the user specifies one or more root modules with "-s" flags, then they will be used as root modules instead.

-Tmin|typ|max Edit

Select the timings to use. The Verilog language allows many timings to be specified as three numbers, min:typical:max, but for simulation you need to choose which set to use. The "-Tmin" flag tells the compiler to at elaboration time choose "min" times. The default is "-Ttyp".

Target Flags Edit

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