This wiki is all about Icarus Verilog.
Icarus Verilog is the popular open source Verilog compiler available here. This Wiki is intended to serve as documentation for Icarus Verilog at a variety of levels of depth, from basic use to detailed internal workings.
That this is a Wiki implies that this documentation is created by the community, and that includes you. So if you have something to say or add, by all means say so and lets discuss it. The "Discussion" tabs lead to talk pages where proposed (and past) edits can be discussed. Individual users (those that log in, at least) also have talk pages that can be scribbled on as well. These are how ongoing work should be coordinated.
Standards For Wiki Authors
This Wiki should be easy to read and easy to follow. The casual reader should experience as much as possible an accurate and polished document. To that end, use these standards to guide you through deciding the appropriateness of what you do.
Use the "Discussion" Tabs
Don't be afraid of the "Discussion" tabs. These are a good place to discuss potential changes, make suggestions, and even see explinations of past changes.
Use the ".v" Suffix for Verilog Files
In the text where you write examples, stick with the convention of using the ".v" suffix for Verilog source file names. There is no technical advantage of this suffix, and there is no suggestion that users must use ".v" on their own time, it's just a matter of internal consistency for the documentation.
Avoid Crazy Fonts
It's very easy in Wikimeda to add all kinds of fonts. It's so very tempting to emphasize a word that seems important at the time, but the result is a cluttered mess of crazy fonts. When in doubt, skip the font gymnastics.
Any other suggestions for appropriate standards? This is a growing document. Presumably, the need for standards will grow with the Wiki itself.
More Information For Authors
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