I am trying to use 2x extensions that allow real model io ports.

The implied syntax, input real name, does not seem to work. Or varients of it.

Anyone have an example?

Try wire real instead of just real. real by itself is a variable definition and normal Verilog does not allow variables as module ports. I plan to add support for wreal eventually, which is from VAMS and may be more portable in the future.

Cary 18:49, September 20, 2011 (UTC)


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